Jia Liu

ECE 3561: Advanced Digital Design
_{^{(Autumn 2023)}}
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Personnel

Instructor: Kevin Liu, Assistant Professor, Dept. of Electrical and Computer Engineering
Contact: 620 Dreese Labs, liu@ece.osu.edu
Time & Location: MWF 1:50PM--2:45PM, Hitechcock Hall 035
Office Hours: Wed 5:00PM--6:00PM
TA: Cedric Le Denmat (ledenmat.1@osu.edu), and Jichao Yu (yu.3608@osu.edu)
TA Office Hours: Thu 5:00PM--6:00PM

Course Topics

- Sequential circuit analysis.
- Timing issues (maximum clock frequency, setup time, hold time, clock skew).
- Sequential circuit design.
- Analysis of sequential circuits with logic building blocks and system controller.
- System controller design.
- More timing issues: asynchronous inputs, glitch-free outputs.
- Design with counters, shift registers multiplexers, comparators, decoders, adders, PLDs, and FPGAs.
- Design technology: VHDL, Xilinx.

Course Materials

- Textbook: C.H. Roth and L.L. Kinney, "Fundamentals of Logic Design," 7th edition, Cengage Learning, 2014.
- Reference Book: John F. Wakerly, "Digital Design: Principles and Practices," 4th edition, Pearson, 2005.

Homework and Computer Projects

- Homeworks will be assigned most weeks. The due date will be explicitly specified on the homework assignment. They will typically be due on the following Monday in class. Solutions will be made available on the ECE 3561 web site after the due date for the assignment.
- Questions regarding grading should be resolved within one week of the time when the graded homework is returned.
- Project 0 is for practice only. Projects 1 and 2 are individual projects. Project 3 will be completed in groups of two, with one report turned in per group.

Exams

There are two midterms and a final exam. Dates for midterms are Oct. 6 and Nov. 20. The date for final exam is tentatively Dec. 13.

Grading Policy

- Attendance: 5%; Homework: 15%; Computer Projects: 20%; Midterm Exams: 30%; Final Exam: 30%

Late Policy

Without the consent of the instructor, no late homeworks will be accepted. In the case of an emergency (sudden sickness, family problems, etc.), an after-the-fact notice is acceptable. But we emphasize that this is reserved for true emergencies.

Schedule

Here is an estimated class schedule, which is subject to change depending on lecture progress and/or class interests. Please check for latest adjustments.

Week	Topics
1	Course Introduction and Overview
2	Clock and Memory; Latches; Analyzing Latches
3	Flip Flops
4	Registers; Buses; Adders; Shift Registers; Counters
5	Design of Counters; MSI Counters; Sequential Circuit Analysis
6	Timing Analysis of Sequential Circuits; Two's Complement Machine
7	Midterm; MSI Components; Two's Complement Machine Analysis
8	Introduction to VHDL
9	Sequential Circuit Design; Details of Synchronous Circuit Design; Minimization of Number of States
10	State and Circuit Equivalence; State Variable Assignment
11	State Variable Assignment; Iterative Circuits; System Controller Based Design
12	System Controller Based Design - Multiplier; Asynchronous Inputs and Output Glitches
13	Memory and Programmable Logic Devices; PLDs; Midterm 2 Review
14
15	CPLDs
16	FPGAs; Final Exam Review

Academic Integrity

This course will follow OSU's Code of Student Academic Conduct. Discussions of homework assignments and final projects are encouraged. However, what you turn in must be your own. You should not directly copy solutions from others. Any reference (including online resources) used in your solution must be clearly cited.

Jia (Kevin) Liu,